A typical linear voltage regulator comprises a transistor, the control terminal of which is connected to an error amplifier. A feedback loop is typically provided between an output from and one input to the error amplifier—the other input to the error amplifier being connected to a reference signal. Parameters which may be important from a design perspective of such voltage regulators include the stability against a variation of supply voltage, and losses in the system. For some applications, the on-chip area required by the voltage regulator can also be an important parameter.
FIG. 1 show a schematic of a typical linear regulator 100. This LDO (low drop out) linear regulator comprises a transistor 10 having a control terminal. A first main terminal, being a supply terminal of the transistor, is connected to a supply input, typically a voltage at a supply voltage Vss. The transistor has a second main terminal being an output terminal configured to provide a regulated output at an output connection, via an output circuit. The output circuit typically comprises a series load resistor Rs. In use a load is connected between the output connection and a ground, which may be a local or global ground. A load capacitance, show as Cload, is also typically connected between the output connection and ground.
The LDO includes an error amplifier 20 having a reference input, a feedback input and an output connected to the control terminal. A reference current source is connected to the reference input for providing a reference voltage at the reference input. The reference voltage typically is set by passing the current Iref from the reference current source through a reference resistance Rref to the local or global ground.
Feedback from the output terminal of the transistor is provided to the feedback input of the error amplifier through a feedback path (which may include a feedback resistance, not shown), for providing a feedback voltage to the feedback input.
In some applications, particularly those for which the LDO is not always operational, it may be advantageous to limit the current to relatively low values. To provide relatively low values of currents, relatively high values of the resistances are required. In the case of LDOs in which the components are all “on-chip”, relatively high values of resistances in turn necessitates relatively large areas of silicon, or high so-called “real-estate”.